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Home  >  Volume 25 (2013)

Design Implementation and Simulation of a 4-Bit Decimal Adder using Parallel Binary Adders and BCD Encoders by Galandanci G. S. M. and Gana S. M. Vol.25 ( Nov. 2013). pp 339-352
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In this work a 4-bit decimal adder was designed, implemented and simulated. The decimal addition is carried out using Binary Coded Decimal (BCD) addition and a 10-line to 4-line encoder was upgraded to 15-lines to 4-lines and was used to convert each decimal digit to its corresponding BCD code.  A 4-bit parallel adder with fast carry (74HC283), and additional circuitry of AND gate and OR gates were interconnected to carry out the BCD addition. A BCD to seven segment display converter (DCD Hex) was used to convert and displayed the generated sum in BCD to decimal. The designed system was implemented and simulated on circuit simulation software (National instrument multisim version 11). The system is tested and found to be capable of performing addition of any two 4-bit decimal numbers.

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